Asicsoc rtl design engineer ai compute platform Vacatures
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Senior/Staff Design Engineer
- Dienstverband
- Overig
- Werklocatie
- Kantoor
- Opleiding
- Overig
- Ervaring
- Ervaren
- Functiegroep
- Techniek & Engineering
- Branche
- Techniek & Engineering
Over de vacature
Overview
In this role you will own RTL design for a new AI compute platform, turning architectural concepts into production-ready silicon. You'll collaborate with architecture, verification and physical design teams to deliver high-performance, power-efficient processor and accelerator blocks. The work spans the full front-end flow from SystemVerilog RTL to tape-out, with a focus on timing, power and integration of IP. This is a hands-on, early-stage opportunity to shape a cutting-edge AI silicon platform in a growing semiconductor company. You'll join a mission-driven team that values ownership and cross-functional collaboration to deliver impactful technology.
Verantwoordelijkheden
- Develop synthesizable SystemVerilog / Verilog RTL
- Translate architecture and ISA requirements into microarchitecture
- Design processor, accelerator and complex SoC blocks
- Integrate internal and third-party IP
- Collaborate with verification, architecture and physical design teams
- Support synthesis, timing closure and PPA optimisation
- Drive CDC / RDC quality and sign-off
- Implement low-power techniques including clock gating, power gating and memory power management
- Support gate-level simulation, FPGA and emulation activity
- Take real ownership of design blocks through to tape-out
Belangrijkste vereisten
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5+ years of ASIC / SoC RTL Design experience
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Strong SystemVerilog or Verilog
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Experience with processors, accelerators or complex SoCs
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Strong microarchitecture experience
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Experience with synthesis and timing-aware RTL design
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Good knowledge of AMBA / AXI / AHB / APB
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Strong CDC / RDC expertise
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Hands-on low-power design experience
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Gate-level simulation and debugging experience
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At least one successful ASIC tape-out
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Experience owning one or more design blocks through the development cycle
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cross-functional collaboration
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ownership
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strong communication
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SystemVerilog / Verilog RTL
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processor/SoC design
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microarchitecture